MOSFET semiconductor devices in which the gate is formed in a vertically oriented groove in the semiconductor material so that current flow is substantially vertical, have been studied recently by several workers in the field. Ueda, Takagi and Kano, in IEEE Trans. on Electron Devices, Vol ED-32 (1985) 2-6, have studied the formation of vertically oriented rectangular grooves by a reactive ion beam etching technique, where the structure manifests reduced on-resistance and high cell packing density. Chang and co-workers, in a series of papers, have also studied formation of vertically oriented rectangular grooves, produced by photolithographic techniques, in semiconductor material and self-alignment of the groove boundaries. See, for example, H. R. Chang, et al., IEEE Trans. on Electron Devices, Vol ED-34 (1987) 2329-2334 and references cited therein. Blanchard, in U.S. Pat. No. 4,767,722, discloses a method for making vertical channel DMOS structures including the use of a vertically oriented rectangular groove filled with doped polysilicon that serves as a gate.
In another research direction, Marcus, Wilson and co-workers have discussed the effects of oxidization on curved silicon surfaces of various shapes, including right angle corners and cylinders and cylindrical cavities. See, for example, Marcus and Sheng, Jour. Electrochemical Soc., Vol. 129 (1982) 1278-1282; Wilson and Marcus, Jour Electrochemical Soc., Vol. 134 (1987). See also Yamabe and Imai, IEEE Trans. on Electron Devices, Vol ED-34 (1987) 1681-1687.
Lidow and Herman, in U.S. Pat. Nos. 4,593,302 and 4,680,853, disclose the fabrication of planar power MOSFETs having hexagonally shaped source cells with hexagonally shaped channels being formed beneath the source region in the semiconductor material.